1. Field of the Invention
The present invention relates to a parallel distributed sample descrambler partfor a cell-based asynchronous transfer mode (referred to hereinafter as ATM) physical layer recommended by CCITT I.432.
2. Description of the Prior Art
Generally, scrambling transmission data at a transmitter side is very useful in data communications as it offers many advantages. The scrambling suppresses continuous generation of the same signal ("1" or "0") to make clock extraction at a receiver side easy. Also, the scrambling randomizes the transmission data to reduce interference effects between codes. At the receiver side, descrambling the scrambled data is performed to recover original information therefrom and transfer the recovered information to the user. CCITT I.432 has recommended a distributed sample scrambler for a cell-based ATM physical layer which is a kind of frame-synchronous scrambler, whose a characteristic polynomial is given by x.sup.31 +x.sup.28 +1.
With the distributed sample scrambler, the scrambling is performed with respect to ATM cell 53 octets, except the 5th octet corresponding to a header error control (HEC) code. Samples of a pseudo random bit sequence (PRBS) generator are taken periodically and transmitted to the receiver side. At the receiver side, PRBS of a descrambler is synchronized with that of the scrambler at the transmitter side using the samples of the PRBS generator.
Using the conventional serial scrambling, there is required a semiconductor device with an operation speed higher than 155.52 Mbps or 622.080 Mbps which is a transmission speed of the ATM physical layer, for the purpose of implementation of the descrambler. However, such a semiconductor device is high in cost and difficult to construct.